1. Field of the Invention
The invention relates generally to semiconductor device fabrication and in particular to the fabrication of field effect transistor (FET) devices. More particularly, the invention relates to opto-thermal annealing methods for fabricating field effect transistor devices.
2. Description of the Related Art
A field effect transistor comprises a gate electrode that conventionally comprises a polysilicon or polycide material. The gate electrode is located upon a gate dielectric. The gate dielectric is located upon a semiconductor substrate. A pair of source/drain regions is located within the semiconductor substrate and separated by a channel region located beneath and aligned with the gate electrode. The basic field effect transistor device structure, as described above, has been successfully scaled to increasingly smaller dimensions for over forty years.
Field effect transistor device performance may be improved by reducing the effective thickness of the gate dielectric. However, continued scaling of field effect transistor devices presents difficulties insofar as further reduction of the physical gate dielectric thickness leads to excessive gate leakage.
Within the context of current gate dielectric thicknesses, it is also desirable to minimize the polysilicon gate depletion effect. Such a depletion effect arises when a polysilicon gate is electrically activated and a region depleted of charge is formed at an interface between the polysilicon gate and the gate dielectric. The existence of such a depletion region reduces capacitance of the gate dielectric and thus increases the effective gate dielectric thickness. As a result of the increased effective gate dielectric thickness, field effect transistor device performance is compromised.
In an effort to eliminate the polysilicon depletion effect, metal gate field effect transistors and fully silicided gate field effect transistors have become of interest. Metal gate field effect transistors and fully silicided gate field effect transistors are readily fabricated by simple substitution of a metal gate or a fully silicide gate for a polysilicon gate. However, a major impediment for implementation of metal gate field effect transistors is thermal stability of a metal gate electrode and an interface between the metal gate and the gate dielectric.
In a conventional field effect transistor manufacturing process, a high temperature of about 1000° C. or greater is needed to activate extension region and contact region portions of source/drain region dopants. During this high temperature dopant activation anneal in the conventional field effect transistor fabrication process, the work function of a metal gate, or threshold voltage (Vt) of the field effect transistor, may shift significantly due to interdiffusion and interface reactions between the metal gate and the gate dielectric. Fully silicided gate field effect transistors may, under certain circumstances, also have thermal exposure limitations.
Since field effect transistor devices are certain to be prevalent within microelectronics fabrication, and since performance of field effect transistors is certainly enhanced with metal gates or fully silicided gates, use of field effect transistors with metal gates and fully silicided gates is certain to continue.